1. Field
The present innovation relates generally to an LC phase-locked loop (PLL), and more specifically to improving the LC PLL's jitter performance, loop bandwidth, voltage control oscillator (VCO) frequency range and the PLL frequency range for multi-speed clocking applications.
2. Background
A phase-locked loop is a well known circuit that is typically used as a control system to generate a signal having a fixed relation to the phase of a reference signal. With reference to FIG. 1, a typical phase-locked loop is shown. The phase-locked loop 100 includes a phase detector 102, a voltage controlled oscillator (VCO) 104, and a feedback 106 path from the VCO 104 to the phase detector 102. The phase detector 102 receives as inputs a reference signal and a feedback signal from the VCO 104. The phase detector output controls the VCO 104 such that the phase difference between the two inputs is held constant. The VCO 104 generates an output frequency based on the output of the phase detector. Voltage controlled oscillators 104 are an integral part of high speed serial interfaces, and the performance of the VCO 104 to a large extent can determine the performance of the PLL 100 as a whole.
With the ever increasing data rates and density of high speed serial interfaces in transmission systems, current Serializer-Deserializer (SerDes) transceivers need to be multi-data rate compatible to support new link speeds and standards while still being compatible with previous speeds and standards. Achieving the desirable higher data rates with older lossy and discontinuous channels places a large burden on silicon, particularly in equalization and clocking. As a consequence, it is desirable to have a low jitter phase-locked loop (PLL) that provides a tolerance in the transmit path jitter budget and also facilitates reliable data recovery by the clock and data recovery (CDR) delay-locked loop (DLL) and phase interpolator (PI) in the receiver.
Typically, when circuit designers attempt to satisfy the requirements of multiple standards with one PLL design, they use a ring-oscillator PLL. The inherent properties of ring-oscillator PLLs give them wide-bandwidth capabilities. However, ring-oscillator PLLs also traditionally suffer from poor jitter performance. Compared to the ring-oscillator PLLs, LC PLLs generally have superior jitter performance but a smaller VCO frequency range. It would be desirable to have a PLL solution with the jitter performance of a LC PLL and the wide-band performance of a ring-oscillator PLL.